The present invention relates to microcomputer systems, and in particular, system controllers therefor. Such system controllers provide control of data flow and address and data timing for microcomputers, which may include more than one microprocessor operating at different speeds with respect to themselves and to other elements of the system.
Microprocessor and memory technologies are advancing rapidly and are expected to continue to advance indefinitely. Moreover, microprocessor and memory technologies are advancing at different rates so that the difference in performance parameters of the microprocessor, the memory and the bus over which they typically communicate tends to expand or contract, i.e., become greater or lesser, as advances are perfected. Thus, performance characteristics of microcomputers employing emerging technologies also advance at different rates.
While present-day microcomputer manufacturers have control over the design and configuration of the systems they produce, they typically must anticipate the parameters necessary for compatibility of their system with add-on peripherals, accessories and memory options produced by other manufacturers. The performance characteristics of such peripherals, accessories and memory options will vary among the manufacturers of these devices. Since the systems for which they were designed also vary, the performance characteristics of such devices are often designed for less than optimum performance, i.e., "detuned". Therefore, the manufacturer of high performance microcomputers must allow for different, even inferior, performance characteristics of peripheral and accessory devices and memory options in order to produce a system which is compatible with the maximum number of devices attachable to the system. If the microcomputer manufacturer does not so anticipate such different performance characteristics, it will limit the marketability of the system to less than the total market available for his product.
A complete microcomputer, which is often intended for desktop applications, includes subsystems such as a central processing unit (hereafter referred to as the "CPU", "processor" or "microprocessor"), a math "coprocessor", dma capabilities, memory, miscellaneous system ports, and interfaces to video, keyboard, floppy disks, serial and parallel ports, scsi devices, and a mouse pointing device.
The microcomputer functions by manipulating address, data, and control signals among the subsystems within the system. The control of system data flow and address and data timing is provided by the system controller which controls the data flow and timing between the processor, main system memory, and the bus.
As faster microprocessor and memory devices became available to microcomputer system designers, increased performance was limited by other components of the systems. For example, the speed of asynchronous bus controller technology could not be expected to increase at a rate commensurate with increasing the speed of the processor and memory devices, even though the speed of the processors and the memory devices were approximately the same and increasing at approximately the same rate. Thus, in the recent past, bus technology was typically limited to a bus cycle of 375 nanoseconds, in a microcomputer such as the PC/AT, manufactured by the IBM Corporation.
If the bus controller were simply driven faster to take advantage of the faster processors and memory devices now available, certain peripheral and ancillary devices would begin to fail in different ways in different systems. The faster the bus controller is driven, the more devices would fail and start to fail. Failure modes include loss of data, address and control signals to a point where response signals, i.e. "handshakes", were not working. Therefore, a microcomputer which would accept faster processor and memory technologies, e.g. 10 or 12 MHz, and still incorporate bus technology operating at 8 MHz is extremely desirable in order to operate with slower peripheral and accessory devices and memory options.
While development of memory components such as Dynamic Random Access Memory ("DRAM") devices have closely followed processor technology, often the control logic for these devices does not. Such logic functions and technology was also a limitation on overall microcomputer system speed. For example, in order for the processor to access memory, access signals must be produced in response to bus controller strobe signals which, in turn, are produced in response to access request signals from the processor. Additive overhead associated with both the bus and memory controllers arising from buffering and gate delays is required to produce these signals. Thus, the need for system memory control to be dissociated from the conventional bus controller is clear, owing to the high degree of interaction with the processor and system memory.
In addition, the design of components for typical microcomputers are relatively old and require longer access times. If the bus controller speed is scaled upwards proportionately, i.e., increased in linear fashion, the relative timing of all of the signals become shorter, certain address setup times and the like cannot be accommodated, and such devices are simply unable to respond.
Finally, the speed of operation of microcomputer subsystems is governed by one or more clock or timing signals which may or may not be synchronized. In the past, such clock signals were usually derived from more than one source which was not synchronized. Thus, when synchronized operation of subsystems was required, tolerances in the timing of control, gating and handshake signals had to be relaxed enough to allow for imprecise cooperation of clock signal source. For microcomputers operating at 8 MHz, performance was acceptable and reasonably reliable.
As operating speed is increased, however, critical system timing parameters must be substantially more precise than can be reliably achieved with multi-source clock signals. Thus, for operation at 12 MHz and above, clock signals produced from one source are required to preclude clock and control signal skewing and provide reliable, high-speed operation.
Separate system memory control according to the present , invention, ancillary to but cooperating with, present state-of-the-art bus controllers, provides 12 MHz processor accessing of 80 nanosecond DRAM available from any number of manufacturers. With the system controller of the present invention, bus timing margins comparable to 8 MHz machines are maintained even when the processor runs at 12 MHz. Therefore, 12 MHz operation has become not only possible, but extremely desirable and cost effective.
In addition, with the present invention, the processor may operate at 12 MHz while the bus provides 375-500 nanosecond cycle times. Moreover, bus cycle times can be selectively varied, manually or under program control, in the present invention, thus providing additional flexibility not available in microcomputers having a conventional bus controller interface among system elements.
In a microcomputer employing the present invention, clock signal generation is derived from a single source. The output of a crystal oscillator is divided by various networks to provide synchronized timing signals for all subsystems of the microcomputer.
The system controller of the present invention includes a bus controller and system memory controller not unlike the bus controller described in copending application for U.S. Pat. entitled "State Machine Bus Controller", Ser. No. 154,641, now abandoned filed on Feb. 9, 1988. Even with the flexibilities described therein, the microprocessor and memory technologies are still rapidly advancing, and are expected to continue to advance beyond the capability of that and other previously known bus controllers. Employing the system controller of the present invention, microcomputer systems may incorporate interactive, synchronous and concurrent system memory and bus control, provide variable bus cycle control and include mapping of address range and processor memory access type to determine bus cycle length necessary for efficient high speed operation.